The present invention is directed to solving the problem of allowing access to instruction memory from a data portion of a pipelined processing system within a split memory architecture. However, to better understand the solution, it is considered important to provide a brief background of a pipelined processing system, and to illustrate the need for a split memory architecture.
Referring to FIG. 1, a block diagram 100 is shown to illustrate instruction flow within a five stage pipelined microprocessor 102. The microprocessor includes: 1) an instruction fetch stage 104 for fetching instructions from memory for execution; 2) a read from register file stage 106, for examining operands within a register file that are specified by the executing instruction; 3) an ALU stage 108, for mathematically, or logically operating upon the operands read from the register file, as specified by the executing instruction; 4) a memory stage 110, to perform loads or stores from/to memory that is external to the microprocessor, such as when an instruction requires that the result of the ALU operation in the ALU stage 108 be stored in memory; and 5) a write back stage 112 to write the result, either from a load in the MEM stage 110, or from an operation in the ALU stage 108, into the register file.
In operation, a first instruction is fetched by the fetch stage 104 for execution during a first clock cycle. During a second clock cycle, the first instruction proceeds to the register file stage 106, and a second instruction is fetched into the fetch stage 104. During a third clock cycle, the first instruction proceeds to the ALU stage 108, the second instruction proceeds to the register file stage 106, and a third instruction is fetched into the fetch stage 104. Thus, at any one time, a five stage processor, such as the one shown in FIG. 1 may have up to five different instructions executing concurrently, each in their own stage within the processor. One skilled in the art will appreciate that modern pipelined microprocessors may have many stages (some have up to 18 stages), each stage executing a different instruction.
So, not only do modern processors execute different instructions at the same time, such as shown in FIG. 1, but often, various stages within modern processors may require access to the same external resources at the same time. Resources that are used by both the fetch stage 104 and the MEM stage 110 include external memory, as well as split instruction and data cache memories. This is particularly illustrated with reference to FIG. 2.
In FIG. 2, a block diagram is shown of a five stage microprocessor 202 such as the one described above with reference to FIG. 1. The microprocessor 202 has five operational stages including a fetch stage 220 and a MEM stage 222 each which requires access to external memory. Access to the external memory is provided via a bus interface unit 224 which is coupled to instruction memory 232 and data memory 234 via an external interface. Whether or not the instruction memory 232 and data memory 234 are separate or unified is irrelevant to this illustration. What is important is that the access to either or both of these memories 232, 234 is through a unified bus interface 224.
The bus interface 224, though it is coupled to both the fetch stage 220 and the MEM stage 222, is only capable of handling a single access request at a time. This does not create a problem if the MEM stage 222 does not require access to the memory 234 at the same time the fetch stage 220 requires access to the memory 232, or vice versa. However, if the fetch stage 220 requires access to the instruction memory 232, to obtain another instruction, at the same time the MEM stage 222 requires access to the data memory 234 (e.g., for a data read/write), then one of the stages will be required to wait while the bus interface unit 224 services the other stage.
It should be appreciated at this point that causing either of the stages within a pipelined processing system to wait, or stall, is not desirable. This is because any delay in one stage of a pipeline affects all the other stages preceding it, and therefore adds to the time it takes for an instruction to execute. This cannot be remedied by simply causing the fetch stage 220 to wait, because the instructions following the fetch stage will continue to execute, thereby creating holes in between the next fetched instruction, and the instructions that preceded it. This is also not desirable.
Therefore, what is needed is a mechanism that allows a number of stages within a pipelined processing system to access memory at the same time.
Moreover, what is needed is a method and apparatus that not only allows concurrent access to memory by different pipeline stages, but one that redirects access from one type of memory to the other as needed.
Furthermore what is needed is a method and apparatus that redirects memory access from a data memory to an instruction memory based on the address of the access requested, and/or based on the type of instruction that is executing.
In addition, what is needed is a redirection method and apparatus for a split instruction/data memory architecture that has an open design, thereby allowing designers of the split/instruction data memory architecture to define for themselves how the memory distinction is made, while simplifying the redirection interface with existing processor side split architecture interfaces.